Dynamic random access memory (“DRAM”) devices are commonly used in a wide variety of applications. One of the most common use for DRAM devices is as system memory in personal computers. The speed and capacity demands on DRAM devices continues to increase in this and other applications. However, power is consumed each time a digital circuit is switched to change the state of a signal line. The rate at which power is consumed by DRAM devices therefore increases with both the capacity and the operating speed of the devices. Thus, the demands for ever increasing memory capacities and speeds are inconsistent with the demands for ever decreasing memory power consumption.
For many applications, it is particularly important to limit the power consumption of DRAM devices. For example, DRAM devices used as system memory in portable personal computers should consume relatively little power to allow a battery to power the computer over an extended period. The limited period over which electronic devices, such as portable computers, can operated has been addressed by both attempts to increase battery life and attempts to reduce the rate at which such devices consume power. Excessive power consumption can also create problems even where DRAM devices are not powered by batteries. For example, the heat generated by excessive power consumption can damage the DRAM devices, and it can be difficult and/or expensive to maintain the temperature of electronic equipment containing the DRAM devices at an acceptably low value.
Various techniques have been used to reduce power consumption in electronic equipment containing DRAM devices. One approach has been to prevent digital circuits from switching when such circuits are not active since, as mentioned above, power is consumed each time a component in the digital circuit is switched from one state to another. While this approach can significantly reduce the power consumed by DRAM devices, there are circuits in DRAM devices that cannot be rendered inactive without compromising the speed and/or operability of the DRAM devices. For example, a computer system may use several registered DRAM modules 10a-c as shown in FIG. 1. Each module 10 includes two DRAM devices 12, 14, although a greater number of DRAM devices may be included in registered DRAM modules. The DRAM modules 10 also include a register 20 that receives control signals coupled through a control bus 24 and address signals coupled through an address bus 26. These control and address signals are latched in the register 20 responsive to an internal clock ICLK signal. The ICLK signal is generated by a phase-lock loop 34 from an external clock (“CK0”) signal, which is applied to the modules 10 though a clock line 35. In one commercially available registered DRAM module, these control signals that are applied to the register include a row address strobe signal (“RAS#”) (the “#” indicates the signal is active low), a column address strobe signal (“CAS#”), clock enable signals (“CKE0” and “CKE1”), a write enable signal (“WE#”) and chip select signals (“S0#” and “S1#”) to activate the DRAM devices 12, 14, respectively. Other signals not latched by the register 20 include the clock CK0 signal, data signals (“DQ0-DQ63”) corresponding to a 64-bit data word applied to the modules through a data bus 28, and a number of other signals that are not pertinent to the present discussion. In this commercially available registered DRAM module, bank address signals (“B0-B1”) corresponding to a 2-bit bank address and row/column address signals (“A0-A12”) corresponding to a 13-bit address are also applied to the register 20 through the address bus 26.
The register 20 used in the registered DRAM modules 10a-c of FIG. 1 is shown in FIG. 2. Each of the control and address signals that are applied to the register 20 are applied to the data input of a respective flip-flop 30. The flip-flops 30 are clocked by an internal clock signal ICLK generated at the output of a phase-lock loop 34. The phase-lock loop 34 receives the clock signal CK0 so that the phase of the internal clock signal ICLK matches the phase of the externally applied clock signal CK0. The use of the phase-lock loop 34 to generate the internal clock signal ICLK avoid excessive loading of the external clock signal CK0 since the clock signal must be applied to a number of circuits in each module 10. The signals applied to the flip-flops 30 are latched on each rising edge of the internal clock signals ICLK.
Returning to FIG. 1, in operation, address signals A0-A12 and the previously mentioned control signals are simultaneously applied to all of the registered DRAM modules 10a-c, and all of these signals are latched into the registers 20 in all of these modules 10a-c. Each module 10a-c receives a different pair of chip select signals that designates which of the modules 10a-c is being accessed. Latching a large number of signals into the flip-flops 30 in each of the several modules 10a-c on each edge of a high speed clock signal can consume a significant amount of power since, as previously mentioned, power is consumed each time a digital circuit switches state. However, only one of the modules 10a-c is selected for a memory access by switching its chip select signals S0# and S1# active low. Therefore, the power consumed by the modules 10a-c that are not being selected for the memory access is unnecessarily consumed. This unnecessary power consumption can be significant since a large number of signals are latched into the registers 20 of each of the inactive modules 10 on each rising edge of the clock signal CLK0, which may have a frequency of 133 mHz or higher.
There is therefore a need for a method and system to prevent power from being needlessly consumed by registered DRAM modules.